Aldec toont op DVCon Europe productreeks voor pre-siliciumverificatie met demonstratie van netwerk-op-chip
MÜNCHEN–(BUSINESS WIRE)– Aldec, Inc., pionier in simulatie met gemengde HDL-talen en verificatieproducten voor systemen en ASIC-ontwerpen, presenteert op de conferentie en expo DVCon Europe zijn productreeks voor pre-siliciumverificatie. De expo vindt 19 en 20 oktober plaats in München.
Op DVCon Europe demonstreert Aldec bewezen verificatiemethodes aan de hand van een ontwerp voor een netwerk-op-chip (NoC). Het ontwerp steunt op onderzoek van Ulf Becker aan de Stanford University. “Het NoC is gebouwd als vermaasde netwerktopologie met een aanpasbaar aantal routers voor verbindende knooppunten”, zei Krzysztof Szczur, hoofd verificatieproducten van Aldec Hardware. “Het netwerk is in staat van het ene willekeurige knooppunt naar een ander willekeurig knooppunt dataverzamelingen te versturen. Hierdoor kan het dienstdoen als backbone van een complex model voor systeem-op-chip-ASIC.”
Aldec to Highlight ASIC Pre-Silicon Verification Spectrum with Network-on-Chip (NoC) Demonstration at DVCon Europe |
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MUNICH–(BUSINESS WIRE)– Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, will present the spectrum of pre-silicon verification solutions at the DVCon Europe Conference and Exhibition to be held October 19-20, 2016 in Munich, Germany. At DVCon Europe, Aldec will demonstrate industry-proven verification methodologies and solutions using a Network-on-Chip (NoC) design based on research conducted at Stanford University by Daniel Ulf Becker. “The NoC was built as a mesh topology with a configurable number of routers that provide device connection nodes,” illustrates Krzysztof Szczur, Aldec Hardware Verification Products Manager. “The network is able to transfer data packets between any pair of nodes and therefore can serve as the backbone of a complex System-on-Chip (SoC) ASIC design.” “Verification of complex designs comprised of NoC structures requires a robust chain of verification methodologies such as static linting, high-performance HDL simulation/debugging, and emulation,” said Louie De Luna, Aldec Director of Marketing. “The Verification Spectrum begins as soon as the first lines of HDL code are available, where designers use static linting to catch common bugs and check code sanity. Then HDL simulation using a UVM Verification environment is completed to achieve the highest level of debugging with Structural and Functional Coverage. Finally, to shorten days or weeks of simulation runs, long test sequences of constrained-random testbenches can be accelerated using an emulator. With Aldec’s 35,000+ user community, Aldec is committed to support every stage of this process.” Visitors to Aldec’s Booth #304 at DVCon Europe will have the opportunity to meet directly with Product Managers who will be on hand to demonstrate an NoC design example, illustrating a seamless verification approach that includes:
About Aldec Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Embedded, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners. View source version on businesswire.com: http://www.businesswire.com/news/home/20161012005159/en/ Contacts Aldec, Inc. |
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